Dear Colleagues,

I wanted to take up this opportunity to briefly point your attention to an academic and scientific driven course with direct implication to our industries: Computational fluid dynamics (CFD) algorithm design with reconfigurable computing course. You can see the official communication at http://www.accelogic.com/training.html.

As I am sure you have read recently, Reconfigurable computing algorithms implemented in FPGAs are 10x to 1,000x faster than traditional parallel algorithms. Many high-performance computing applications are turning to FPGAs and reconfigurable computing to squeeze performance for their biggest computational challenges.

Although the algorithm implementation cycle in reconfigurable computing is similar in principle to that of a traditional software solution (code program, debug, compile, test), mastering the art of reconfigurable computing requires a paradigm shift in the thought process of the algorithm developer. Under this new paradigm, you free yourself from the limitations imposed by an instruction-based machine architecture (known in the literature as the "von Neumann or software bottleneck"), and open the door to a liberated world, full of opportunities for the discovery of new and groundbreaking algorithms, in which you can manipulate the machine architecture to best solve your problem.

The aim of this course is to disseminate this cutting edge technology among the scientific, research and industry professionals that can benefit directly from it.

If you think you might be interested, please let me know how I can help you finalize your registration process. However, if you are not planning to attend, I would appreciate your feedback as to what can be done to make your participation possible for this session, or future ones of similar content.

I sincerely appreciate your time and responses. Should you have any questions whatsoever, please do not hesitate in contacting me.

Sincerely,

Beatriz Navarro Accelogic Phone: (954)249-4761 Email: bnavarro@accelogic.com

Hi,

Interesting idea - but nothing to do with CFX (at least for many years yet).

Glenn Horrocks

Its rather more than a "good idea". Von Neuman arches are now fundamentally power limited.

Ansys ought to be ivestigation FPGAs in house.

http://video.google.com/videoplay?do...81475&q=engedu

Hi Joe,

OK, it is a very good idea. But still we won't be seeing it in CFX for many years. It is a paradigm shift away from current mainstream computing technology and that takes years before it becomes commonly available.

Glenn Horrocks

The high performance computing group at my company have been "investigating" Clearspeed (www.clearspeed.com) FPGAs for a couple of years now. Mainly for physics and engineering simulation apps. I believe we looked at various in-house and commercial codes we have the src code for.

Not sure what the current progress is, but having attended the programming course for the clearspeed processor the biggest problem was having to code in Assembly to realise the potential benefits of using these processors. Not sure if this has changed.